As is well known, a solid state drive (SSD) is a data storage device that uses a NAND-based flash memory to store data. The NAND-based flash memory is a non-volatile memory. After data are written to the flash memory, if the system is powered off, the data are still retained in the flash memory.
FIG. 1A schematically illustrates the architecture of cells in the flash memory of a solid state storage device. The flash memory 105 has a memory array composed of plural cells. Generally, each cell of the flash memory 105 has a floating gate transistor. During a program cycle of the flash memory 105, hot carriers are injected into the floating gate of the floating gate transistor. By controlling the amount of hot carriers to be injected into the floating gate, the threshold voltage of the floating gate transistor can be changed. Consequently, the storing state of the cell is determined according to the threshold voltage. During an erase cycle, the hot carriers are ejected from the floating gate of the floating gate transistor. The memory array comprises plural word lines WL(n−1), WL(n) and WL(n+1) for controlling respective rows of cells. When one of the plural word lines is activated, the cells in a selected row corresponding to the activated word line are programmed.
Depending on different designs, the flash memories are classified into single-level flash memories (SLC) and multi-level flash memories. The multi-level flash memories include double-level flash memories, triple-level flash memories or more-level flash memories.
FIG. 1B schematically illustrates the threshold voltage distribution curves of the various flash memories in different storing states. The single-level flash memory can store only one bit of data per cell (i.e., 1 bit/cell). According to the amount of the hot carriers injected into the cell, each cell of the single-level flash memory has two storing states corresponding to two threshold voltage distribution curves. For example, the cell with the lower threshold voltage has the storing state “0”, and the cell with the higher threshold voltage has the storing state “1”. The storing state “0” and the storing state “1” are two different storing states. Moreover, the storing state “0” also indicates a first storing state, and the storing state “1” also indicates a second storing state. For example, the cell with the threshold voltage of approximately 0V has the first storing state, and the cell with the threshold voltage of approximately 10V has the second storing state.
The double-level flash memory can store two bits of data per cell (i.e., 2 bits/cell). According to the amount of the hot carriers injected into the cell, each cell of the double-level flash memory has four storing states corresponding to four threshold voltage distribution curves. According to the threshold voltages in ascending order, the storing states of the cells include the storing state “00”, the storing state “01”, the storing state “10” and the storing state “11”.
The triple-level flash memory can store three bits of data per cell (i.e., 3 bits/cell). According to the amount of the hot carriers injected into the cell, each cell of the triple-level flash memory has eight storing states corresponding to eight threshold voltage distribution curves. According to the threshold voltages in ascending order, the storing states of the cells include the storing state “000”, the storing state “001”, the storing state “010”, the storing state “011”, the storing state “100”, the storing state “101”, the storing state “110” and the storing state “111”.
In other words, during the program cycle of the flash memory, the threshold voltage and the storing state of the cell are correspondingly changed by controlling the amount of the hot carriers injected into the cell. For programming the single-level flash memory, a single program procedure is required to program the cells to the desired storing states. However, for programming the multi-level flash memory, many program procedures are required to program the cells to the desired threshold voltages and the desired storing states.
FIG. 2 schematically illustrates an approach of programming a triple-level flash memory. The triple-level flash memory is also referred as a TLC flash memory. In FIG. 2, three program procedures are performed to program the cell of the TLC flash memory to the storing state “100”. Firstly, in the first program procedure, the cell is programmed to the threshold voltage near the storing state “111”. Then, in the second program procedure, the cell is programmed to the threshold voltage near the storing state “101”. Then, in the third program procedure, the cell is programmed to the threshold voltage corresponding to the storing state “100”.
In other words, it is necessary to realize the final storing state of the TLC flash memory during the program cycle. For programming the cell of the triple-level flash memory to the storing state “011”, the cell is programmed to the threshold voltage near the storing state “000” in the first program procedure, then the cell is programmed to the threshold voltage near the storing state “010” in the second program procedure, and finally the cell is programmed to the threshold voltage near the storing state “011” in the third program procedure. The ways of programming the triple-level flash memory to other storing states are similar, and are not redundantly described herein. Generally, for programming the multi-level flash memory, plural program procedures are required to sequentially change the threshold voltages of the cells. Consequently, the threshold voltages of the cells are programmed to be in the desired threshold voltage range.
As mentioned above, it is necessary to perform plural program procedures to program the cell to the desired threshold voltage during the program cycle of the multi-level flash memory. If the number of times of programming the cells does not reach a predetermined value, it means that the data to be stored into the cells are not completely stored into the cells. Under this circumstance, the data to be stored into the cells cannot be read out from the cells.
Generally, the flash memory comprises plural blocks. Each block contains plural pages. During the program cycle, data are written into at least one page of the flash memory. The size of the page is defined by the manufacturer of the flash memory. For example, the size of each page is 2K bytes, 4K bytes or 8K bytes. For example, the write data of the 4K-byte page containing user data, encoding data and associated data have a total of 4224 bytes (=4224×8 bits).
In other words, a total of 4224×8 single-level cells of the single-level flash memory are required to store the data of a 4K-byte page. Since the data density of the double-level flash memory is higher, a total of 4224×8 double-level cells of the double-level flash memory can store two pages of data (=2×4224 bytes). Similarly, a total of 4224×8 triple-level cells of the triple-level flash memory can store three pages of data (=3×4224 bytes).
Moreover, each word line of the flash memory is connected with 4224×8 cells. Consequently, the 4224×8 cells can be programmed simultaneously. For example, in the triple-level flash memory, the cells connected to each word line can store three pages of data. Moreover, three program procedures are required to program the cells connected to each word line. However, in some kinds of multi-level flash memories, the cells connected to the same word line are not subjected to multiple consecutive program procedures during the program cycle of the multi-level flash memory. Hereinafter, a method of programming this multi-level flash memory will be described by taking a TLC flash memory as an example.
FIG. 3 is a schematic functional block diagram illustrating a conventional solid state storage device. As shown in FIG. 3, the solid state storage device 300 comprises a controller 301, a buffer 307 and a TLC flash memory 305. The controller 301 is connected with the buffer 307 and the TLC flash memory 305. Moreover, the controller 301 is connected with a host 320 through an external bus 310. Consequently, commands and data can be exchanged between the controller 301 and the host 320.
A process for writing host data from the host 320 to the TLC flash memory 305 will be illustrated as follows. Firstly, the controller 301 performs an error correction (ECC) encoding operation on the host data, encodes the host data into host write data, and stores the host write data into the buffer 307. Then, the controller 301 performs the program action at proper time in order to store the write data in the buffer 307 into the TLC flash memory 305. For example, the buffer 307 is a static random access memory (SRAM) or a dynamic random access memory (DRAM). When the supplied power is interrupted, the data temporarily stored in the buffer are not retained in the buffer 307. Generally, the external bus 310 is a USB bus, an IEEE 1394 bus, a PCIe bus, an SATA bus, or the like.
Moreover, according to the specifications of the multi-level flash memory, the program order of the TLC flash memory 305 can be determined. FIGS. 4A and 4B schematically illustrate the program order of the TLC flash memory. For example, the size of one page is 4K bytes. In addition, the write data of the 4K-byte page containing user data, encoding data and associated data have a total of 4224 bytes (=4224×8 bits).
Generally, the TLC flash memory 305 comprises plural blocks, and each block comprises plural pages. Moreover, three pages of host write data are stored in the cells corresponding to the same word line. In FIGS. 4A and 4B, an open block of the TLC flash memory 305 and the program procedures of the cells connected to the corresponding word lines are described. When the open block is full, the controller 301 sets the block as a closed block. Then, the controller 301 searches another blank block of the TLC flash memory 305 and sets the blank block as an open block. Then, the host write data are stored into the open block according to the similar program order.
Please refer to FIG. 4A again. After the host data with 12 pages are received by the solid state storage device 300 and the ECC decoding operation is performed on the host data, 12 pages A-L of host write data are generated and temporarily stored in the buffer 307 sequentially.
As mentioned above, the cells corresponding to each word line of the TLC flash memory 305 can store three pages of data. As shown in FIG. 4A, the host write data of the pages A, B and C are stored in the TLC cells corresponding to the first word line, the host write data of the pages D, E and F are stored in the TLC cells corresponding to the second word line, the host write data of the pages G, H and I are stored in the TLC cells corresponding to the third word line, and the write data of the pages J, K and L are stored in the TLC cells corresponding to the fourth word line.
According to the specifications, the program order of the TLC flash memory 305 is shown in FIG. 4B. Firstly, the controller 301 activates the first word line and performs a first program procedure (1st). Then, the controller 301 activates the second word line and performs a second program procedure (2nd). Then, the controller 301 activates the first word line and performs a third program procedure (3rd). Then, the controller 301 activates the third word line and performs a fourth program procedure (4th). Then, the controller 301 activates the second word line and performs a fifth program procedure (5th). Then, the controller 301 activates the first word line and performs a sixth program procedure (6th). Then, the controller 301 activates the fourth word line and performs a seventh program procedure (7th). Then, the controller 301 activates the third word line and performs an eighth program procedure (8th). Then, the controller 301 activates the second word line and performs a ninth program procedure (9th).
The program order of FIG. 4B complies with the following rules. In the TLC flash memory 305, the TLC cells corresponding to a specified word line are completely programmed after three program procedures are performed. As shown in FIG. 4B, the TLC cells corresponding to the first word line are subjected to the three program procedures after the sixth program procedure is performed by the controller 301. That is, after the first program procedure (1st), the third program procedure (3rd) and the sixth program procedure (6th) are performed, the three program procedures of the TLC cells corresponding to the first word line are completed. Consequently, the threshold voltages of the TLC cells corresponding to the first word line are in the desired threshold voltage ranges of the host write data of the pages A, B and C. Under this circumstance, the host write data of the pages A, B and C are stored in the TLC cells corresponding to the first word line.
That is, after the first program procedure (1st), the third program procedure (3rd) and the sixth program procedure (6th) are performed, the controller 301 confirms that the TLC cells corresponding to the first word line are completely programmed. Meanwhile, the host write data of the pages A, B and C are stored in the TLC cells corresponding to the first word line. Similarly, after the second program procedure (2nd), the fifth program procedure (5th) and the ninth program procedure (9th) are performed, the controller 301 confirms that the TLC cells corresponding to the second word line are completely programmed. Meanwhile, the host write data of the pages D, E and F are stored in the TLC cells corresponding to the second word line.
If no new host data are provided by the host 320 after the ninth program procedure (9th), it means that no new write data are added to the buffer 307 to be stored into the TLC cells corresponding to the fifth word line of the TLC flash memory 305. Due to the limitation of the program order of the TLC flash memory 305, the controller 301 cannot perform the subsequent program procedures on the TLC cells of the third word line and the TLC cells of the fourth bit line because the controller 301 cannot perform the program procedure on the TLC cells of the fifth word line. In the TLC flash memory 305, the TLC cells corresponding to the third word line are only subjected to two program procedures, and the TLC cells corresponding to the fourth word line are subjected to only one program procedure. Consequently, the TLC cells corresponding to the third word line and the TLC cells corresponding to the fourth word line are not completely programmed. Therefore, the host write data of the pages G-L are not completely stored in the TLC cells corresponding to the third word line and the fourth word line.
After new host data from the host 320 are converted into the host write data and stored into the buffer 307, the controller 301 performs associated control operation again according to the program order. Consequently, the TLC cells corresponding to the third word line and the TLC cells corresponding to the fourth word line are sequentially programmed. That is, after an additional program procedure is performed, the TLC cells corresponding to the third word line are completely programmed. Moreover, after two additional program procedures are performed, the TLC cells corresponding to the fourth word line are completely programmed.
Generally, after the TLC cells corresponding to a specified word line are completely programmed (i.e., subjected to three program procedures), the controller 301 can perform an error correction (ECC) encoding operation to accurately read the stored data. Whereas, if the TLC cells corresponding to the specified word line are not completely programmed (i.e., not subjected to three program procedures), the desired threshold voltages of the TLC cells are not achieved. Under this circumstance, the stored data cannot be accurately read from the TLC cells through the ECC encoding operation of the controller 301. For example, if the TLC cells corresponding to the third word line are not completely programmed, the stored host write data corresponding to the pages G, H and I cannot be accurately read from the TLC cells through the ECC encoding operation of the controller 301.
As mentioned above, the TLC cells corresponding to the third word line and the fourth word line as shown in FIG. 4B are not completely programmed. After the other new host write data from the host 320 are provided, the controller 301 continuously performs associated control operation according to the program order of the TLC flash memory 305. That is, after the TLC cells corresponding to the third word line and the TLC cells corresponding to the fourth word line are completely programmed, the corresponding stored data can be accurately read.
When a flush command is transmitted from the host 320 to the solid state storage device 300, the controller 301 has to confirm that all of the temporarily-stored host write data in the buffer 307 have been completely stored in the TLC flash memory 305. That is, the controller 301 has to confirm that all of the cells storing the host write data from the buffer 307 have been completely programmed. Then, the data temporarily stored in the buffer 307 are cleared by the controller 301.
As shown in FIG. 4B, if no new host data is transmitted from the host 320, and when the flush command from the host 320 is received by the solid state storage device 300, the controller 301 will self-generate redundant write data, temporarily store the redundant write data into the buffer 307 and perform the program procedures to store the write data from the buffer 307 to the TLC flash memory 305. Consequently, the host write data of the pages G-L in the buffer 307 can be completely stored into the TLC cells corresponding to the third word line and the fourth word line.
FIG. 5A is a flowchart illustrating a data writing method for a conventional solid state storage device. This flowchart describes the action of the solid state storage device 300 in response to a flush command. Normally, in response to a write command from the host 320, the controller 301 receives the host data, converts the host data into the host write data, and temporarily stores the host write data into the buffer 307.
In the step S502, the flush command from the host 320 is received by the controller 301. In order to store the temporarily-stored host write data in the buffer 307 into the TLC flash memory 305, the controller 301 generates redundant write data and temporarily stores the redundant write data into the buffer (Step S504). Then, during a program cycle, the write data in the buffer are stored into the open block of the TLC flash memory 305 according to the program order by the controller 301 (Step S506).
FIGS. 5B and 5C schematically illustrate the program order of the conventional solid state storage device in response to the flush command. The storing condition of the flash memory 305 is similar to that of FIG. 4B. In the situation of FIG. 4B, the flush command from the host 320 is received by the solid state storage device 300.
Please refer to FIGS. 5A and 5B. In order to store the temporarily-stored host write data in the buffer 307 into the TLC flash memory 305, the controller 301 generates six pages of redundant write data Ra˜Rf and temporarily stores the redundant write data into the buffer 307.
Please refer to FIG. 5C. Then, the controller 301 performs the program action. Consequently, the write data in the buffer 307 are stored into the TLC flash memory 305 according to the program order.
That is, the controller 301 activates the fifth word line and performs a tenth program procedure (10th). Then, the controller 301 activates the fourth word line and performs an eleventh program procedure (11th). Then, the controller 301 activates the third word line and performs a twelfth program procedure (12th). Then, the controller 301 activates the sixth word line and performs a thirteenth program procedure (13th). Then, the controller 301 activates the fifth word line and performs a fourteenth program procedure (14th). Then, the controller 301 activates the fourth word line and performs a fifteenth program procedure (15th).
Obviously, after the fifteenth program procedure (15th), the TLC cells corresponding to the third word line and the TLC cells corresponding to the fourth word line have been completely programmed. That is, when the flush command is received by the conventional solid state storage device, the controller 301 generates and temporarily stores the redundant write data into the buffer 307. Then, the controller 301 performs the program action to store the write data in the buffer 307 into the open block of the TLC flash memory 305 according to the program order.
As mentioned above, when the flush command from the host 320 is received by the solid state storage device 300, the controller 301 has to generate the redundant write data and temporarily store redundant write data into the buffer 307. If the host 320 continuously issues the flush command during the process of transmitting the host data, the controller 301 has to generate the redundant write data, temporarily store redundant write data into the buffer 307 and store the redundant write data into the TLC flash memory 305. FIG. 6 schematically illustrates the data storage conditions in the flash memory of the conventional solid state storage device. As shown in FIG. 6, the host 320 continuously issues the flush command during the process of transmitting the host data. Consequently, the host write data (Ho) and the redundant write data (R) are alternately stored in the open block of the TLC flash memory 305.
As known, the redundant write data (R) are invalid data. If the host 320 continuously issues the flush command during the process of transmitting the host data, the number of the invalid data stored in the TLC flash memory 305 gradually increases. Under this circumstance, the utilization efficiency of the solid state storage device 300 decreases.